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Recent content by cloudz88

  1. C

    How to set the core_gen signal ?

    Re: core_gen hahas...u saw my project meh?? mr lai show u 1?? did he say anything about it?? actualli there are some flaws in the project...but i tried to cover it up..hahas..dun tell him worx.... mr lai didnt say anything on the last day...he juz say.."ok lahs...can...u can go now...good...
  2. C

    How to set the core_gen signal ?

    Re: core_gen jason here..wahaha...finally i graduate le.... u...better look after the newcomer worx...=D
  3. C

    Simple IF loop question

    if i use If loop......and i need to put in 2 condition.....how should i write? if ( condition 1 & condition 2 ) then . . . end if; liddat?? some1 pls help..
  4. C

    VHDL dual port RAM help

    true dual-port ram in vhdl ermm...if i use If loop......and i need to put in 2 condition.....how should i write?
  5. C

    VHDL dual port RAM help

    ram inout port vhdl sorriex..i dun realli understand the codes given by Ram i read this from some forum....issit impossible to write and read on the same address location?
  6. C

    VHDL dual port RAM help

    ram+in+vhdl heres the program....i zipped it Port A to Write and Port B to Read...
  7. C

    VHDL dual port RAM help

    dual port ram vhdl is there a delay when i write into the address array or when i read from the address array...........??
  8. C

    VHDL dual port RAM help

    dpram vhdl i use coregen to generate a dual port Ram... i wrote Data into AddrA 0,1,2,3,4,5,6,7,8,9 but when i read the data from AddrB... AddrA 0 = AddrB 3 instead of AddrB 0 AddrA 1 = AddrB 4 AddrA 2 = AddrB 5 . . . . AddrA 9 = AddrB 12 is like..the data doesnt match wif the address...
  9. C

    How to write data on the dual port RAM?

    i realli having some trouble with my final year project.... i created a dual port Ram V6.3 using Core Generator but i realli dunno how to write data into the Dual Port Ram i have already declare and assign all the pins already but i still stuck at programming part... can some1 help mi??
  10. C

    How to write data to address array of dual port RAM using VHDL?

    Re: VHDL Dual port Ram does i need to do any declaration for the mem?? i notice ppl use "Width -1 downto 0" and "Depth -1 downto 0" what is the main purpose of that??
  11. C

    How to write data to address array of dual port RAM using VHDL?

    Re: VHDL Dual port Ram what does it mean by mem(conv_integer(address_0) ???
  12. C

    How to write data to address array of dual port RAM using VHDL?

    Can some1 gimmi the VHDL coding of....how to write data into the address array?? please....really in need....thanks lotsa
  13. C

    What does ADDR[A|B] mean?

    ADDR[A|B]<m:0> i dun realli understand the <m:0> its from dual port ram...>_<''
  14. C

    how to solve this error?? anybody know?

    vsim 3732 default binding # Loading work.ram0(ram0_a) # ** Error: (vsim-3732) assignment2a.vhd(78): No default binding for component at 'u2'. # (Port 'dout' is not on the entity.) # Region: /testbench/u1/u2 # Loading...
  15. C

    FYP lend me a hand ^^ thanks everyone

    wat type of wave are u lookin for?
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