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Recent content by cloudius

  1. C

    help on high speed op/comparator design

    do i need a 160MHz clock to control track-latch??
  2. C

    help on high speed op/comparator design

    op comparator wiki input signal:20mv@160MHz sine wave output:digital signal (pulse wave) which circuit should I use?
  3. C

    where can i get disciplines.vams???

    disciplines.vams and constants.vams my hspice cant compile verilog ams files without those two files.
  4. C

    Which OS platform is better suited for Cadence design tool SE?

    cadence OS platform rh9 suse10 RHEL4
  5. C

    any good paper on static comparator

    dynamic comparator use clk ,tgate and caps to select input
  6. C

    Help me to simulate INL and DNL using Cadence

    INL,DNL measurement use verilog-a to sim.those code i found from a post here...icant find link.. // VerilogA for TEST_ADC, inldnlmeasure, veriloga // $Date: 2005/11/25 // $Revision: 0.0 $ // Static perfomance ADc mesure // Accuracy depend from dLSB=S*T/LSB // S -slope of ramp // T -...
  7. C

    how to define Vcm in pipeline AD design?

    vcm ota i've read lots of pipeline A/D papers.Vcm appears oftenly in comparators ,OTA and S/H circuit schematics. and i'v got confused at the definition and magnitude of Vcm. Is Vcm a fixed value under certain VDD?? or Vcm should be caculated form circuit?? has Vcm relateto OTA,S/H or other...
  8. C

    laterally diffused field effect transistors

    advantage demos drain extended good post
  9. C

    TSMC design kit for C@dence

    site:edaboard.com tsmc design kit cant download??? Added after 3 minutes: Added after 1 minutes: ???
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