Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by cloud9Z9

  1. C

    [SOLVED] verilog beginner for loops

    U mean LD_PC[18]. Anyway thanx for the quick reply.
  2. C

    [SOLVED] [new] verilog operator

    thanx for the quick reply
  3. C

    [SOLVED] verilog beginner for loops

    /*-------------- LD_PC -------*/ /**/ /**/ initial begin /**/ /**/ //-- Initialize to 0. /**/ for( i = 0; i < 64; i = i + 1) begin /**/ LD_PC[i] = 1'b0; /**/ end /**/LD_PC[18]=1'b1; /**/ //-- Set non-zero as needed. /**/ end can i do this ?? i just need to set LC_PC[18] to 1.
  4. C

    [SOLVED] verilog beginner for loops

    module fori(A,B); input [0:5] A; output [0:5] B; wire [0:5]A; reg [0:5]B; reg i=0; initial begin for(i=0;i<6;i=i+1)begin B[i]=A[i]; end //B[4]=1'b1; end initial begin $monitor("OR=%b, AND=%b, IN=%b, time=%t\n",B,A,$time); end endmodule module tb_fori(); reg [0:5]A; wire [0:5]B1; fori...
  5. C

    [SOLVED] [new] verilog operator

    what does out = (in+1)%(1<<16); mean ?? both in and out are 16 bit busses. I understand in+1 but why % 1<<16?
  6. C

    [SOLVED] [new1] verilog beginner

    Solved it thanx guys....A is declared as a register when it is used in the procedural statements and used a wire in combinational logic statements
  7. C

    [SOLVED] [new1] verilog beginner

    /* Verilog for cell 'test1{sch}' from library 'testlib' */ /* Created on Thu Dec 08, 2011 18:43:01 */ /* Last revised on Fri Dec 09, 2011 01:01:37 */ /* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */ module test1(A,B,C); input [0:2] A; output B...
  8. C

    [SOLVED] [new1] verilog beginner

    /* Verilog for cell 'test1{sch}' from library 'testlib' */ /* Created on Thu Dec 08, 2011 18:43:01 */ /* Last revised on Fri Dec 09, 2011 01:01:37 */ /* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */ module test1(A, B, C); input [0:2] A; output B...
See more

Part and Inventory Search

Back
Top