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well ok i got everything working
also did the long divison algorithm
now my true aim was to make lcm calculator
so i did everythin but this line is not working
int3<=int3+int3;
where int3 is std logic vector signal (5 downto 0)
ok thnx fvm
i got that working .
that having separate state for assignement was helpful
but as u guys told yea it is a lengthy process
so i did what permute said but now again the output comes 0
heres the code for long division
entity long is
Port ( clk : in STD_LOGIC;
reset : in...
ok i found out the problem with my program now i only some one can help me to debug it
the problem is each time the state changes
these two statements are excuted again
int1 := conv_integer(c);
int2 := conv_integer(d);
and reset their values
so is their a way i can set int1 and int2 ouside of...
@kunalvyas155
Well i tried that but still it didnt work for no where state change is required
it worked for 3 and 4 but not 3 and 8
@permute - well can u provide a lil vhdl snippet of what you are saying cuz as you can see i am having problem with the rapid changes of states here
#edit
ok this...
i am making a vhdl code for finding remainder
i know there is a mod operator but still i am making the following program
the problem is suppose i divide 4 by 3 so in this case i have to subtract 4 by 3 only once so the program shows the necessary output
but lets say a loop is needed (for which i...
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