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Recent content by cklin

  1. C

    How to implement interpolation using verilog coding

    interpolator verilog You must design the algorithm first. You need design a filter and interpolate input data by insert zero or repeat the input.
  2. C

    Why active low reset are used in Verilog?

    Re: Active low reset Most library supply active-low reset DFFs. It seems that larger noise margin exists in low states.
  3. C

    What is the best book for DSP Algorithm in Telecommunication

    Re: What is the best book for DSP Algorithm in Telecommunica I recommend what cat_basilio recommended. It is a helpful and has been uploaded in this forum.
  4. C

    what tools used in system-level verification

    C/C++ If it is related to digital signal processing, SPW/Cossap/Matlab/Simulink can do.
  5. C

    Why use PrimeTime when DC can do timing analysis..?

    PT is more powerful than DC,such as case analysis or SI analysis. Meanwhile, PT is faster than DC.
  6. C

    What are the best simulation tools for ASIC?

    Re: asic simulation ASIC:verilogXL or NCverilog FPGA:modelsim
  7. C

    Noise shaping filter - any suggestions?

    Re: Noise shaping filter I think sigma delta modulation is the only choice. Good Luck
  8. C

    What differences between direct form FIR and transpose FIR

    fir direct form transposed form transposed form is self pipelined with the cycle period the delay of an adder and a multipiler. But it has more area than directed form. You can add delay even in directed form or transposed form to make the design faster which resulted in mixed form. But you...
  9. C

    what is the type of output of the FIR filter?

    sigma-delta ADC includes two parts,analog sigma-delta modulator, after the modulator, digital signal generates, then you decimate the digital output from the modulator using digital filter, finally improved quantized multibit digital signal generates.

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