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Re: DIVA
You need to write a rule file that includes all the parasitics information required. I'm not an expert when it comes to writing these rule files, but you should be able to find or request documentation from Cadence.
Re: DIVA
DIVA RCX (R-C-eXtraction) is a module of DIVA that is, depending on the setup provided, able to extract parasitic R's and C's. Check which switches are availabe when you open the RCX menu.
Regards,
Chris
Re: ESD Transistor: Why the pitch contacts of the Drain shou
Hi electronXwork,
I have never come across any paper etc. that would have recommended to use a larger pitch for the contacts in the drain region. Logically, it makes no sense as one would want to have as many contacts as possible...
Re: about fuse?
Hi shrbht!
Poly fuses work like a PROM. The user can fuse (literally burn) poly connections and thereby store information. Poly fuses can be programmed once.
Metal fuses- also called laser fuses- are metal connections that can be fused by cutting the metal line using laser...
Hi diemilio,
DIFF is Field Oxide (FOX). So where ever you draw DIFF, there WON'T be any FOX growth. Please let me know if you need further explanation!
Regards,
C.
Re: multiple vias
Aditionally to the above answers, yield is also a factor for placing multiple vias or contacts. Especially contacts often cause yield problems in sectors where failures are practically unacceptable (eg. automotive). Some place&route tools are capable of doing post- routing via...
Re: Minimum density Rule
Hi,
usually, foundries provide special filling runsets withtheir design kits to meet minimum densities on metal and poly. Most of the time, it is a DRC Runset which creates floating dummy rectangles on each layer and saves it as a cell. Look for such a runset in your...
Hi leohart,
generally, if you have a robust bond stack, it shoud be sufficient to use just one metal to connect the pad. For supply pads, the topmost (usually the thickest) metal should be used. On another note: in some processes it is advisable not to use a minimum width metal trace to connect...
Of course you have to stick to your design rules when it comes to via size. Most CMOS processes will only allow a fixed via size.
The stack of a bond pad should always be made up of at least all metal layers available in order to withstand vertical forces during the bond process and to add...
Re: About electron migration
You are correct. AlSi is more prone to e- migration than AlCuSi/AlCu or "pure" copper. However, several methodes are used to minimize the effect in Al metallizations. Ti/TiN or Ti/TiN/Ti liners for example are used for W- vias and contacts or even on top and bottom...
Re: Antenna Effect
I see there is still some confusion about the antenna effect. Let's try an example:
Your design rules state that the maximum ratio of a given metal layer to gate- poly is 3000/1. Assuming we have a minimal gate connected to a very long metal1 trace which exceeds this ratio...
Re: Antenna Effect
Correct, charge will only accumulate at the metal layer to be etched as this is the metal being in direct contact with the plasma. I understand your concern about the small metal area jumering eg. metal1. But what is important is the area of metal directly exposed to plasma...
pcm wafer test data
The process control monitor (PCM) refers to the suite of test structures usually placed in the scribeline (alternatively named kerf, street or test key) separating product die on the wafer.
These test structures include such for measuring electrical parameters of active...
I'm by far no expert on simulation models, but I can tell you that new gate stacks for >=45nm are based on hafnium oxides and metal gates with engineered work- functions for nmos and pmos. Both work- function engineering and totally new hafnium oxides in combination with low-k dielectrics (!)...
Re: Antenna Effect
You cannot ignore antenna effect for gates! My statement was referring to diffusions. So generally, I don't see any danger for diffusions of minimal transistors in these tech nodes. What you have is basically a diode structure, as the substrate of the wafer is held at a...
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