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Recent content by chris_li

  1. C

    Anyone who know ARM synthesized product like Cortex-A8S?

    It is Cortex-A8S rather than Cortex-A8, "S" here represents "Synthesized".
  2. C

    When to enable OCV, after CTS immediately or timing-clean?

    Hi Guys, would you share experience?
  3. C

    block-level's clock_insertion_delay and top-level's CTS?

    If I have a hierarchy design on hands with brief information as below * top-level has three subblocks(A, B and C) * only one main clock, period is 2500ps * data path: primary input->A->B->C->primary output After each subblock PnR independently, each of them has around 1000ps...
  4. C

    Do you remove "set_driving_cell" and "set_load" when taking over SDC file from FE?

    Do you remove "set_driving_cell" and "set_load" when taking over SDC file from FE? Hi Guys, it is said back-end guys usually remove certain constraints like "set_driving_cell" and "set_load" from SDC file if any prior to loading it to PnR tool, really?
  5. C

    <magma talus> reg2out path check result mismatches PT?

    Hi Jeevan, Here is the header of report from Talus, pls note clock period is 5000ps while output_delay is 2000ps Reference arrival time ******************** 0 + Cycle adjust (clk:R#1 vs clk:R#2) ********5000 - Setup time************************ -2000...
  6. C

    <magma talus> reg2out path check result mismatches PT?

    Yes, computed(propagated) mode, after "fix clock"(CTS built) even the same result after "fix wire". I run at the block-level rather than top-level, I guess talus does not update latency or other reasons. I assume the entire path should be "reg2out(A block) -> in2reg(B block)", and there is no...
  7. C

    <magma talus> reg2out path check result mismatches PT?

    Hi Guys, I found, in default, "data required time" of reg2out path for talus built-in timer does not account for "clock network delay"(terminology of PT). In simple, it calculates "data required time = clock period - output_delay" while PT do in such way: "data required time = clock period +...
  8. C

    set_input_delay and set_output delay

    Childs, yes, in this case, buffer should be inserted to fix the violation like "removal" issue of reset path(in2reg).
  9. C

    <magma talus> how to allocate each routing layer cost?

    Hi Guys, anyone who know how to allocate routing layer cost in Talus? I mean, I found lower layers like Metal1, Metal2 has heavy cost (probably timing concern by inter-connect thru lower layer) while higher layer has an even low utilization. It causes lower layer congestion and quite more DRC...
  10. C

    <Magma Talus> partial placement blockage against congestion area

    I did an experiment of placement between ICC and Talus. For ICC, I can distribute congested area to get a relatively even placement by using partial placement blockage as a result. But for talus, there is an interested phenomenon: firstly, congestion spot is slightly different between each time...
  11. C

    <Magma Talus> about global router

    For common APR tools like ICC, SOCE and Talus, global router is usually invoked during placement stage and run in incremental mode until detailed router turn on. However, compared with ICC and SOCE, I found few issues of Talus global router (probably it is Talus' weakness), that Talus sometimes...
  12. C

    To keep ICG at high level of clock tree, any better way to fix "EN" setup violcation?

    To keep ICG at high level of clock tree, any better way to fix "EN" setup violcation? Hi Guys, as you know, placing ICG clock gate cell at higher level as possible in clock tree, the better for power saving. However, it might introduce setup violation of "enable" pin of ICG. May I have you good...
  13. C

    Using Encounter for multi-corner driven PnR, where to get tech file of RC chars?

    Got it with thanks, but I mainly mean "RC corner" rather than "PVT corner"
  14. C

    Using Encounter for multi-corner driven PnR, where to get tech file of RC chars?

    Using Encounter for multi-corner driven PnR, where to get tech file of char'ed RC? Hi, in the case of multi-corner driven PnR, RC at different PVT/Corners has the different value which asks tool to cover. However, where to get such tech file including characterized RC value at different...
  15. C

    What is the difference between a .lib and a .db file used for Design Compiler?

    .lib is ASCII file while .db is binary file
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