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jagz,
The setup and hold time are caused by the gates present in the master latch. Remember the latches that constitute the master-slave are level sensitive than edge sensitive. so as long as the clock is high, it latches the input. the data presented at input of master takes some time to reach...
Even if you are doin a chip level synthesis, you will have external designs that interact with your design. Hence it is required to meet timing for this path ie.
reg of external design -> o/p pin of external design -> i/p pin of your design -> reg in your design.
The constraint values are...
I can try to xplain this in contxt of an ARM SoC..
once the Soc reset is deasserted, the ARM starts booting. While Booting ARM jumps to the location 0x00 which is the reset vector location. From there It loads each instrucrtion from ROM one by one.. you can observe the Addresses fetched by ARM...
Maybe DC is not removing the assign statements because you have set dont touch on some modules or the clock/reset networks. in that case you will have to replace the assign statements manually/using scripts
can you try initializing all registers before you start the simulation run. Basically make sure all flip-flops have some valid value (0 or 1 NOT x) at the beginning of simulation.
The x can also appear if you have multiple drivers for the same signal.
@pps: Deciding factor for WHAT?
setup is deciding factor for "calculating max frequency". The design wont work properly if you have setup or hold violations on the path. But you can avoid the setup voilation by operating at a lower frequency which is not possible in the case of hold violations.
I'm hearing the term for first time. Few minutes of googling tells me this: A new approach to verification which is a mix of formal verification and simulation. It is a coverage driven simulation where the un-covered parts of code in simulation is detected and input stimulus are generated...
Setup is decidin factor to calculate the max frequency at which the circuit can work.
But hold violations are more serious because you cannot make the circuit work by reducing the frequency.
Critical path is the path in the circuit that has maximum timing violation or that has maximum delay. So the frequency of the circuit is dierctly dependant on the critical path and hence its analysis.
False paths are those paths which may be physically present, but logically, it may be an...
Re: design verification.
Pre-silicon verification is very important in ASIC design flow. It is a very costly affair to prepare the masks and fabricate the design on Silicon. hence we try to uncover the bugs even before they are made into silicon. More late the bug is caught, the more costlier...
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