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memory in verilog
HI ,
i have a doubt in memory which is defined...in the above reply...
if the ram is to be designed for 1kb of 8bit then syntax is [7:0]ram[0:1023] right ?
instead of [15:0]ram[0:1023]!!!
i think it is [7:0] instead of [15:0]? :?: :?:
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