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Recent content by Chethan Chethu

  1. C

    Ucf file conversion from virtex-2 to virtex-5

    **broken link removed** This link would be fine i guess..
  2. C

    Ucf file conversion from virtex-2 to virtex-5

    this is for virtex-5
  3. C

    How to plot BER manually?

    ok thank you greygoo, how bout PSNR calculations for a matrix, eg: 3x3 matrix(input and output)..?? n wat is the concept regarding AWGN(white noise)..?? do they use any pseudo random generators to generate the noise.??
  4. C

    Ucf file conversion from virtex-2 to virtex-5

    yeh i understand and i know that two different board pins can't be same.. bt my question is that what are these vga pins in virtex-5..?? vga pins Virtex-2 << vga_comp_synch vga_h_sync vga_v_sync vga_out_blank vga_out_pixel_clock>> vga pins in Viretx-5 << VGA_IN_CLAMP VGA_IN_COAST...
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    Ucf file conversion from virtex-2 to virtex-5

    Hi, i have written code for vga interface with Virtex-2 board.. Now i need to use the same code for virtex-5 board with slight changes in .ucf file.. But the signal lines are a bot different in both.. especially "vga_out_pixel_clock" line.. can any one help me..?? UCF of Virtex-2: #PACE: Start...
  6. C

    How to plot BER manually?

    ok thank you greygoo, how bout PSNR calculations for a matrix, eg: 3x3 matrix(input and output)..?? n wat is the concept regarding AWGN(white noise)..?? do they use any pseudo random generators to generate the noise.??
  7. C

    How to calculate PSNR for image input.??

    How to calculate PSNR for input image matrix by using MSE eqautions..?? please help me out...
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    How to generate AWGN.??

    Can any one tell me how to generate AWGN signals manually and its concept.. and wat are the calculations required for generating noise..??
  9. C

    How to plot BER manually?

    thank you for d help in BER.. But wat bout the formula BER= erfc(sqrt(Eb/No))..?? how do we calculate using dat formula.? what is d errorfunction(erfc) in dat.? plzz...
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    Is there an IP core available in Xilinx software for VGA interface with FPGA.??

    Thank you dpaul.. will find it out but i have another doubt regarding BER calculation. i know manual calculations and even through matlab/simulink.. but how to calculate using the formula BER= erfc(sqrt(Eb/No))..?? what is d errorfunction(erfc) in dat.? and confused with PSNR calculations as...
  11. C

    How to plot BER manually?

    thank you for d help in BER.. But wat bout the formula BER= erfc(sqrt(Eb/No))..?? how do we calculate using dat formula.? what is d errorfunction(erfc) in dat.?
  12. C

    Is there an IP core available in Xilinx software for VGA interface with FPGA.??

    Yeh exactly dpaul i have input data in ROM which i need to send through AXI IP or any available IP and i need the output in VGA display.. But in dat IP there are many I/O signals.. dnw hw to send video data into AXI IP.. - - - Updated - - - Hi shaiko, we can use vivado even for 5series.. but...
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    Is there an IP core available in Xilinx software for VGA interface with FPGA.??

    FPGA: Virtex-5 and 7.. i have both with me.. actually i have designed an DWT based OFDM system in Verilog using Xilinx14.4. Simulation results are coming from the system but have some problems in implementation i.e., VGA interface because my input is image data. Infact i have verified the output...
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    Is there an IP core available in Xilinx software for VGA interface with FPGA.??

    thank you all.. bt i would like ask it more precisely now.. my doubt is dat " Do we have any option in Xilinx or Vivado to generate an VGA stand alone IP or can it be done by integrating other IP's like AXI n others.?? for example we create an DCM/ DDS/ ROM stand alone IP's.. Similarly for VGA.?
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    Is there an IP core available in Xilinx software for VGA interface with FPGA.??

    Is there an IP core in Xilinx software for VGA interface.?? if so please let me know.... Thanks in advance.
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