Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
sorry,rca,
I did not mean adding another inverter,
what i want to say is, in the following two condition, why the second one has the small delay
1. two inverter close to each other
2. two inverter far away from each other.
but thank you though
thank you for your patience
thanks a lot,
by the way, I am wondering that when i doing sta using the primetime toool, do I needs the sdf file, ?
It seems that the sdf is output file for functional simulation , right ?
thank you so much, rca
but actually my question is to fix the set up time issue, we should reduce the delay,
thus, why not place two inverters close to each other but further to each other,
as we all known that, long wire means more delay
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.