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Hi,
I have read in some articles that subthreshold leakage current is a major problem faced by designers in lower process nodes like 65nm and 45nm. I would like to understand the physics behind this phenomena.. Why does it increase with decrease in Vt? Can anyone give me an intuitive or...
Hi,
I would like to know how to get the BGR output accuracy interms of ppm/degreee Celcius. I think for a 1.2 V BGR, 1 ppm = 1.2 uV. If my total BGR output variation is 12 mV across the temperature range -40 to 125, then what will be my accuracy?
yeah.. you are right. I coudnt bias the cascode transistors. Either the pmos or the nmos cascode goes into linear region. I want to use it for a BGR. Can I use this architecture to design a folded cascode with gain boosting? bcoz when I go for gain boosting, I cant use current mirror right? Do...
Hi,
I am not connecting a current ,oad at the output.
Like for an opamp, you can use a resistive load, current mirror load or a current source load right. So, in my circuit, I have used a cascode current mirror load. If I want to use a current source load, then I am not able to bias. Hope I...
Hi,
I have tried to design a folded cascode. The schematic and AC response are attached with this mail. I have 2 questions:
1. The PhaseMargin is very poor. Can you help me to understand how to
improve PM . Is it bcoz I havnt connected load cap (Cl)?
2. I am able to easily bias the...
Hi,
I have tried to design a folded cascode. The schematic and AC response are attached with this mail. I have 2 questions:
1. The PhaseMargin is very poor. Can you help me to understand how to
improve PM
2. I am able to easily bias the transistors if I use a pmos current mirror...
Hi,
Thanks for a clear explanation on how to find the positive and negative terminals for opamp.
So, In the BGR schematic I have attached, IN1 is the inverting input and IN2 is the non-inverting input right?
Then, I think my feedback is wrong.. bcoz I think I should connect the signal in the 2...
Hi,
I have seen in many circuits that a BJT is used in place of a diode by shorting the base and collector. Is there any particular reason behind this? What are the problems faced by designers if a PN Jn. diode is used in place if diode connected transistor?
Hi,
I have a basic question. How to indentify the positive and negative terminals for opamp?
Like in my case, I want to find the + & -ve terminals for the single stage pmos input diff pair.
Hi,
Thanks for your help. Whatever way I adjust the resistors, I am getting only an inverted bell shaped curve, just the opposite of the normal ones which I see in the books. Is there any problem in my toplology due to which I am getting such a curve?
Thanks a lot. After using the bgr+res combination at ouput, I am able to get the reference output. Pls refer to attached ckt. Hope its correct :)
I did a DC sweep of temperature but curve doesnt look like the normal one. Where am I going wrong?
I think you are asking why there is no BJT in the path from which I am taking 'Vref' output....
I referred to ckt in Allen & Hollberg book and tried to use it. Is it wrong?
The reference is ckt is attached with this mail.
You are right. After interchaning the opamp inputs, its working fine. Can...
Hi,
I could get a gain of 63dB and PM=30.
I actually wanted to used this opamp in BGR. So, I tried the basic BGR topology but I am not able to force same value to both the inputs of opamp. The current mirror load transistor is going out of saturation. I am not sure if the feedback method I am...
I have tried the basic BGR topology but I am not able to force same value to both the inputs of opamp. I am not sure if the feedback method I am using is correct.
Can anyone check my schematic and tell me where I am making mistake...
How is the opamp output normally fedback.. I coudnt get any...
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