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hi, it's been some years I'm doing RTL simulation.
when I run ncsim, the wave file (trn) file is generated with incrementing numbers like below.
ckim@stph45:~/Neuro/convhw] ls tb_conv.shm
tb_conv-1-1.trn tb_conv-3-1.trn tb_conv-5-1.trn tb_conv-7-1.trn
tb_conv-1.dsn tb_conv-3.dsn tb_conv-5.dsn...
to my ncvlog -debug tb_conv.v I got
ncvlog: 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
ncvlog: *F,INVDBX: invalid debug license.
- - - Updated - - -
Oh, I should have give -access rwc to ncelab command.
Hi,
It's been years since I worked on Verilog design last time.
To do a simple test, I tried running Verilog simulation and I get this warning during simulation. and I can't see the signals in simvision window.
The line I get this error is marked below (by '<=== here')
initial begin...
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