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Recent content by chandrasg

  1. C

    problem with assign in verilog

    Not in this case. If you try using non-blocking assignments in always loop with clock you may see the difference.
  2. C

    problem with pll lock during ATPG simulations

    Define the PLL Initialization in spf so that pll lock happens before ATPG starts in your patterns. As rca suggested, you dont need PLL to be active in ATPG stuck at tests. You can configure the PLL in bypass mode for stuck at and drive all clocks externally from ATE. If your tester cant...
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