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Shitansh,
I understood what is jitter,skew,setup margin and latency.But can you tell how to calculate the input and output delay constraints for logic synthsesis.I am getting the formulas evrywhere i browse but i didnt get any explanation for that.
Can you tell how the input delays and output delays are calculated in presence of jitter,skew and setup margin.Dont give just the formula.Its available evrywhere but it is bit hard to interpret them..
hello shivram sir,
sir do you mean to say that the target library contains the the transistor technology level information related to the cells in the link library.So when the link library takes a sub-design in a design.the link library would based on the reference and cell names would link to...
go to this link:
dc_shell.html
or hit :"design compiler ug" in google searchbar.Down load design compiler ug1 to design compiler ug9 ..there would be many user guides but they are not useful and very high brow.Thats what i felt.Download these pdf.It is helping me very much.
-chandrakant
`timescale 10ns/100ps
module clk;
reg clk_1,clk_2;
initial
begin
clk_1=1'b0;
end
always #10.10 clk_1=~clk_1;
according to this timescale the clk will toggle after 10.10 * (10ns/100ps) units i.e. 1010 units .
So to generalise it, no matter what what is the unit of time just divide...
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