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Recent content by castrader

  1. C

    I can't load state in cadence5141 base on centos4.7

    to load states Hi i can't load state in spectre when working on cadence5141 though i have save the sate, and the state can be found in .artist_states who can tell me why?and how to solute it? my working system is centos4.7
  2. C

    How to perform a dither archi for 1-bit sigma-delta adc?

    I am afraid if dither is too large to keep quantizer overloading, how to select dither amplitude?
  3. C

    How to perform a dither archi for 1-bit sigma-delta adc?

    How to generate random code? How to define dither voltage level? I know that dither level is about LSB/2, I want to know how to get this level. Can anyone give me some advice or architecture or papers? Also can anyone tell me when design it, what need I take care mostly? Thank you very much!
  4. C

    analog comparator design and phase margin

    analog comparator design Normal analog comparator need not care PM, but if for T-H use that comparator must hold, form feedback loop, you must take care to it.
  5. C

    What does the A-weighted term mean?

    120 dB, A-weighted for audio band 20-20kHz, gain is about 0dB other band, gain is attenuated much. a-weighted @1kHz gain=0dB 1kHZ<signal<5kHz gain>0dB, max gain is about 2-3dB, other range gain<0dB
  6. C

    which differential amplifier configuraion should i choose?

    N-input-pair better for high input cm level, and your working freq is high, also you need only drive cap loads, so 1-stage folded-cascode is good for your design. Take care to your GBW and SR.
  7. C

    is Post Layout Simulation necessary for 0.35 process analog

    functional check is needed. and if your circuit working freq is much more than 10Meg. you'd better do postsim for RC-extraction netlist.
  8. C

    Do any guys know what's the principle of cutting AC loop?

    I want to know where to cut the loop to do a AC simulation? I cut the LDO loop in same point with AC analysis and stb analysis of spectre seperately, but find the different result, obviously, the stb results is more acceptable, I want to know why my AC analysis is failed?
  9. C

    How to implement a variable resistance in CMOS process

    why not use MOS transistor as a R?
  10. C

    What define Cgb Cdb in hspice simulation? Help!

    i think cgd cdb cgs is include in the models not in the spice file. you can use lx18 - lx34 see it (details in hspice mannual)
  11. C

    Looking for book: CMOS op-amp and comparator book by Greogorian.

    Help needed search Greogorian you can get it
  12. C

    why ADC always choose SC cmfb

    sc cmfb will generate great equivalent resistance, so that it will not affect the output stage gain. Also by sc cmfb, other voltage than vcm can be feedback to the op, so that one cmfb op can be saved to enhance the cmfb gbw. The most fundermental reason is that: ADC is a discrete time block, it...
  13. C

    Some questions about the attached OPAMP

    the right part is a floating-current mirror classAB amplifier I donot know why the left part's top is connect to VOUT
  14. C

    how to simulate a sigma delta ADC properly?

    It's not removed, but is your level isnot enough
  15. C

    How to increase CMRR of a telescopic opamp?

    opamp pay attention to the tail current source! Its rds is the most important!
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