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how to black box the submodule in dc
Since your analog block is treated as a black box, and it's interface timing is represented by ILM model, I think you can use set_input_delay/set_output_delay on top-level ports as usual.
specman tutorial
Thanks for above replies. I do also think specman e is more powerful and popular. It's strange that my manager asks us to setup verification environment using vera.
My maneger said the reset bypass mode is only used for internal debug, and the error is caused by our SDRAM simulation model, so it can be ignored in real application.
This issues is closed now.
Thanks for farmerwang and IanP's kindly reply.
We do implement remap in our SOC. The flash is remapped to address 0x0 when boot up.
Then the remap is cleared, and SDRAM is initialized. After that, the processor moves code from flash to SDRAM, and executes code from SDRAM later.
To farmerwang...
The general design flow is introduced in the book I mentioned.
Following is our design flow . Please note that iterations exist in practice.
design specification
|
design architecture ( referring to other similar design)
|
RTL coding...
The book Application-Specific Integrated Circuits, by Michael John, is good introduction book, which covers the whole ASIC design from front-end to back-end, and can be found in internet.
Our SOC is embedded an ARM CPU. It's strange that the reset signal of SRAM controller must be de-asserted before CPU reset, or the system can't be boot up. Does anyone know the reason? Thanks in advance.
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