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Recent content by carrie

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    Help me understand metastability hardened flip-flops

    Re: MetaStability Aviodance attached is a good paper
  2. C

    set_input_delay and set_output_delay in primetime

    how to black box the submodule in dc Since your analog block is treated as a black box, and it's interface timing is represented by ILM model, I think you can use set_input_delay/set_output_delay on top-level ports as usual.
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    Which one is better Vera or Specman?

    specman tutorial Thanks for above replies. I do also think specman e is more powerful and popular. It's strange that my manager asks us to setup verification environment using vera.
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    Which one is better Vera or Specman?

    Can anyone tell me which is more popular, powerful, and easy learned? thanks.
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    need the manual of the ASTRO OF Synopsys

    what is reference synopsys astro lab manual Asrto user guide part2. version is 2003.03.
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    need the manual of the ASTRO OF Synopsys

    synopsys astro guide Astro user guide. hope it helpful. part1
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    SDRAM controller question

    My maneger said the reset bypass mode is only used for internal debug, and the error is caused by our SDRAM simulation model, so it can be ignored in real application. This issues is closed now.
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    How to use the ASIC libraries during synthesis (Synopsys)?

    Re: ASIC libraries Since Pad cells are instatanced directely. The pad ring module is only linked in top level during logic synthesis.
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    Differences between Hercules and Calibre

    hercules vs. calibre Calibre is preffered.
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    SDRAM controller question

    Thanks for farmerwang and IanP's kindly reply. We do implement remap in our SOC. The flash is remapped to address 0x0 when boot up. Then the remap is cleared, and SDRAM is initialized. After that, the processor moves code from flash to SDRAM, and executes code from SDRAM later. To farmerwang...
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    Need recommendation for Backend design Ebooks/Docs

    The general design flow is introduced in the book I mentioned. Following is our design flow . Please note that iterations exist in practice. design specification | design architecture ( referring to other similar design) | RTL coding...
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    What's the best way to do Regression Testing?

    Yes, Perl scripts and C shell are feasible method. I once used them to setup software QA regression.
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    verilog coding style:IF,ELSE VS case?

    Style two is a better way for faster speed, more readable.
  14. C

    Need recommendation for Backend design Ebooks/Docs

    The book Application-Specific Integrated Circuits, by Michael John, is good introduction book, which covers the whole ASIC design from front-end to back-end, and can be found in internet.
  15. C

    SDRAM controller question

    Our SOC is embedded an ARM CPU. It's strange that the reset signal of SRAM controller must be de-asserted before CPU reset, or the system can't be boot up. Does anyone know the reason? Thanks in advance.

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