Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you PlanarMetamaterials and moh.haroun!
More doubts follows!
1. Why is only TE10 mode considered in a waveguide (dominant mode; I know! Any particular reason?)? Why not TE20 or TM11? Is it because more connectors/probes are need for exciting/detection?
2. How does one excite the...
Upon exciting a structure via wave-ports/lumped ports, how does HFSS differentiate between signal and ground conductors? How can one assign them separately? I thought, integration line was responsible for differentiating between these two. But, it is not!
For example, if one has a 2 plate...
As a start, we implemented a basic CMOS inverter for a 50 Ohm output port impedance. We used a common drain buffer amplifier for matching purposes. But, the width of the buffer had to be increased to impractical values. This was compared to an inverter response with a high output port impedance...
mtweig, can you please provide us with a simple circuit diagram of "cascaded inverter with common mode feedback". All that comes into our mind is NMOS and PMOS tied to form an inverter and cascaded. What is the common mode feedback in inverters? We are working on MOSFET/VLSI circuits for the...
Thanks pragash for your reply! We are not encouraged to design Hartley or Colpitts oscillator. The power consumed must be very low.
What kind of a buffer can help us in implementing a high input impedance, low output impedance, low power consuming circuit?
Thanks FvM and ydtech for your replies!
I get it, like an Op-amp, or a common drain amplifier! Am I right? These have high input impedance and low output impedance. But isn't the power gain high for a common drain amplifier? This will lead to a high power dissipation, isn't it?
Can you please...
OK! Now that I have drawn your attention, let me explain. :wink:
I had posted this problem earlier in the following post: https://www.edaboard.com/threads/343243/.
1. We have a Ring VCO which outputs for a high port impedance of 50 KOhm. At 50 Ohm the output is pulled towards the ground. The...
I followed the AWR manual for importing the netlists to AWR. You have to add additional commands so that AWR can parse the model parameters. https://awrcorp.com/download/faq/english/docs/Users_Guide/importing_netlists.html
Try importing the TSMC 180nm model parameters with the .subckt command...
The phase noise plot obtained for a Ring VCO for TSMC 180nm technology is shown below. This was obtained after adding the following CMOS parameters with noise parameters added;
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.23 TNOM = 27...
After adding transmission lines to represent interaction between DGSs, and after a bit of optimization for its length and width, i am obtaining a frequency response as shown below:
Is the modeling correct? What more do I add to achieve a perfect response? Also, how to extract the lumped...
Hi,
The S-parameters for a DGS band-stop filter by EM simulation in shown in the figure below.
The band-stop model can be easily extracted by parallel RLCs. The figure attached below shows the equivalent RLC circuit model with its frequency response.
But the S11 poles or reflection zeros...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
