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Recent content by caecar

  1. C

    about clock skew - how to do data delay?

    Thank your good and fast repliy! In my design,there's 1 system clock,and it was div 3 clock signal.then skew was done. 20.48M(system clock) div=>2.048 div=>512k =>64k
  2. C

    What is a good starting point for FPGA design?

    re where can i get many good E-book about FPGA design?
  3. C

    about clock skew - how to do data delay?

    about clock skew in my design , clock skew > data delay in many path,how can i do ? my chip is altera's cyclon ,and soft is Quartus.
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