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Recent content by cadenceguy

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    Errors after running DRC for digital ICs

    Re: drc for digital ic Std cells are designed for partictular process. Is the error in the block itself or between overlapping blocks? Ie Via_cell Does your Manual & DRC deck have the same values ? Usually the DRC is more comprehensive, but may generate false errors. Make sure that you are...
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    Difference betwn .tf and .lef files

    Re: tf and lef All, There is Techonology LEF & Macro Lef The Tech-lef contains process info (ie: met1 Width & space & construct of vias) the macro lef contains the "abstract" of the layout leaf cell. (Usually looks like Met1 with Pin & blocking data included) Have fun ! Colin
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    where can i get layout design software?

    microwind/ cadence software based projects Ledit is PC based ( not very useful) Iced is PC based (Very storng) magic Linux Cadence expensive.
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    How to invoke "AutoRoute" by using SKILL functions

    Re: How to invoke "AutoRoute" by using SKILL funct Put in your "do" file.. ie: route 25, cleaan 7
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    Reducing the noise in analog circuit with layout technique

    Re: layout and noise Ambreesh, If you are trying to seperate a noisy area from a quite area then each should have its own route back to the pad. Unless of course you have multiple power pads. Dont use the same GND-metal to connect noisy areas with quite areas even though they connect thru...
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    Calibre can't point out all the same error, why?

    They are right .. look for max error and change..
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    full custom layout design

    Use the book ART OF ANALOG LAYOUT by Alan Hastings.. I teach Layout
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    Layout Expert looking for work

    Have expertise in Analog/RF/Digital/APR Email for resume if interested.. cadenceguy@comcast.net
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    I met difficulty when transfering library to another foundry

    Re: I met difficulty when transfering library to another fou Pplus & Nplus are color reverse. (straight cmos) You can use the Generate layer function in cadence to generate data. Turn on Background Add new layer Nplus In Generate layer Dropdown do this on test cell Nplus = Background AND NOT...
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    ask a question about top metal

    O.K. I've got it !! The are "touch-points" for microprobing de-passified parts.
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    I/O cell and connection zone distance

    Depends on your packaging house.. A safe rule of thumb is 1/3 bond pad opening. ie: if pad = 90 , then space should be around 30.. 20 if you want to push it.. This is a generic rule. I've got 24 years doing layout.. this is my conclusion. ;')
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    Reducing the noise in analog circuit with layout technique

    Re: layout and noise I suggest using "star" power & GND. On the n+ guard rings , add nwell , with a width 2x as wide as minimum. the minimum width does not let the nwell go as deep as a wider width. Tie the N+/NWELL to positive supply .. ie: Analog power.
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    How to enable antenna DRC on Cadence?

    metal bridge antenna drc I've been doing layout 24 years.. 1)The best way to resolve the antennae problem is to add a p-diode over nwell or a n-diode over psub on the metal1 node that attaches to the gate. The idea is that the diode will break-down before the gate-oxide. This is an absolute...
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    Need a Layout guy ? 24 years exp!

    I am A Cadence expert. Analog/Digital Layout All verification tools. Diva Dracula Calibre Chameleon Back annotation. APR for resume Send e-mail to cadenceguy@comcast.net
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    Does "Cadence_SOC4.1_for_linux" support Place and

    icc stands for IC-Craftsman ,licenced from Mentor.

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