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Recent content by Bubs23

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    Usage of always inside a function in Verilog

    Hi All, I know this a very basic question i am posting.But i need correct answer for this.Can we write functions in verilog using always block.Can functions contain always block.Please explain it with an example.This is the question asked put to me in many interviews. Thanks, Bubs:-o
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    [SOLVED] connecting modules in verilog

    Just write another module with different name and port lists.Are your ports bidirectional?
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    Explain the working of SONET/SDH in detail

    Hi Sumati, SONET/SDH is a huge topic which cant be explained over the forum.The basics i can share with you.SONET/SDH protocol is very useful in data transmission over communication medium.Transmission over a communication medium has various factors to be taken into consideration like frame...
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    Translate verilog code to vhdl code...

    Hi you can use a VCS tool also to simulate your VHDL code.
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    macros in physical design

    Hi Chandra, I am sorry.I am aware of the macros in methodlogies like OVM/VMM/UVM. Thanks, Bubs
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    macros in physical design

    Hi Chandra, May i know are you asking about macros in methodologies? Thanks, Bubs.
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    vest institutes for embedded systems and vlsi in Hyderabad

    Hi, There is an institute for VLSI called Veda IIT.Its like an MS course.Its for 2 years and very good institute.I don't have idea about Embedded Systems. Thanks, Bubs
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    OVM based environment for VIP

    Hi All, Can anyone explain me how exactly we can develop a VIP based on OVM environment and what exactly does it mean? Thanks, Bubs.:!:
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    AMBA4 AXI Protocol-Master

    Hi All, i am presently working on AMBA AXI4 protocol.i am looking for help on Master.Can anyone help me how to start with it and what are its design specifications. Thanks In advance, Bubs
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