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Recent content by bubber1974

  1. B

    How can I implement a asyn ram in Xilinx ?

    how to use ram in xillinx The only way is to use flip flop's (i.e. CLBs)
  2. B

    a problem about configuration for xilinx FPGA using a CPLD

    It might be possible to burn the FPGA, if you pull the PROGRAM pin low for extended periods of time. I've never experienced any problems related to that, but the Xilinx data sheets mention the problem.
  3. B

    Schmitt input for xilinx's spartan2 design.

    Is it at all possible to configure Spartan II-IOBs as schmitt triggers? I don't think so!

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