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Recent content by bteddy1

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    verilog .V file errors "Verilog HDL Implicit Net warning"

    File is attached. What is wrong? How do I fix it? `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:27:41 05/06/2011 // Design Name: // Module Name: stepper // Project Name: // Target...
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    Help identify symbols from Quartus RTL view.

    I have only seen adders as squares with A, B, Cin, Cout, Sum out. I have never seen a circle. What type of adder is it? Is hfc - high frequency clock or something else?
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    Help identify symbols from Quartus RTL view.

    Hello, Need help with a couple symbols in a Quartus RTL view. In the attached jpg I have drawn the symbols. Questions: What circuit is the circle with the plus in it representing? What does the 10'H 200 mean? The output is ten bits but only eight are shown going to input D. Are all ten bits...
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    Help with Terms in .V file

    Reading a Verilog .v file it defines circuits in a FPGA. Correct? So, ena would equal a Enable signal line. rst would equal Reset signal line. I just need a little help defining: cmps = ???? needs clarification (is it a comparator OR a chip-multiprocessor OR a complex...) fmod = ???? needs...
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