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Hi t4_v,thank you for your reply.
First of all, your transistors are big thus their matching should be improved just by that. The problem can be the length that I guess is the minimum length and is equal to 0.7 um, thus it can be a little problematic in Monte Carlo and the matching can worsen...
Hi,
I am new to analog layout ,I am working in Cadence.
I want to make matching layout for current mirror consisted of two identical mosfets, 240/0.7um.I am planing to make 4 mosfets of 60/0.7um of each mosfet in mirror,and then to use 1D common centroid. In Art of analog layout from Alan...
eagle dspic33
isn't the voltage in gtp lite hardware for programming dspic too high,in datasheet they say it can't be over 13,2V,and with this schematic you get 13,5V
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