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Recent content by brunope

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    [SOLVED] Uncomplete RC network

    So, to complete the explanation: -there were also some shorts on the gds, and looking at the routing, we could see that it was because of lack of routing space (we are using only few metals, and a lot of routing blockages for analog signals. By enlarging the floorplan, everything got fixed...
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    [SOLVED] Uncomplete RC network

    Hi guys, sorry for the delay. To keep you posted, yes, you were right, my design has problems. We were facing congestion problems, and the gds generated had plenty of problems. We enlarged slightly the floorplan, and all the Errors are gone. Indeed, Encounter is not very recent (2014), but...
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    [SOLVED] Uncomplete RC network

    Hi timof, Tanks for taking hte tme to explain this in detail. What I get in the SPEF header is : *VENDOR "Cadence Design Systems, Inc." *PROGRAM "Encounter" *VERSION "14.28-s033_1" I'm reporting this point to the guy taking care of the integration of this digital block in Virtuoso. This is...
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    [SOLVED] Uncomplete RC network

    Hi Timof, Thanks for your message. So if I get your point correctly, the rc extract is fixing the rc network, and therefore, the connectivity check does not report any Error. Is it correct? Should I then run the connectivity check after the routing but before the RC extract. I checked the...
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    [SOLVED] Uncomplete RC network

    Thanks for this advice.That's what I did and I can't find anything relevant. I'll dig further there...Thanks
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    [SOLVED] Uncomplete RC network

    Thanks for your comment, I ran a connectivity check, and it reports no Error... How can I check this problem after routing? Thanks
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    [SOLVED] Uncomplete RC network

    Hi guys, When running the RC extraction with Encounter at the end of the PnR flow, I get the following messages: **ERROR: (ENCEXT-3423): Detected 2 nets with incomplete RC network. Low-value resistances have been added by the software to complete the RC network of these nets. Review the list...
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    Question about post cts encounter negative insertion delay

    Question about post cts encounter negative insertion dealy Hi all, I have been doing some ASIC back end flow for some time now, but I am discovering Cadence tools... I am facing at the moment something that I don't understand with Encounter. In post cts stages, in the report timings in...
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