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Recent content by brunoaduarte

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    Asus AC Adaptor (Output: 19V) - Model AD890026 stopped working after drop

    Hi @Relayer, thanks for the reply! I've inspected all the pcb with a magnifying glass couple of times, there seems to be no issue at all with the pcb. The solder point you marked is not broken, it's just a lack of solder on the right side of the pin, the left side is totally soldered (anyway i...
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    Asus AC Adaptor (Output: 19V) - Model AD890026 stopped working after drop

    Hi! My Asus AC Adaptor (Input: 100-240V / Output: 19V) - Model AD890026 that stopped working after a drop. - I've checked the fuse and it's ok. - Made a visual inspection and all the solder seems fine. - Removed and tested the yellow MPX40 part with a multimeter and it measures 283.7 nF - The...
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    Smal size GSM and GPS modules - SMD

    Re: Smal size GSM and GPS. Hello Stian, i'm also looking for small GSM module, and it seems the GE865 is the smallest available. I have one question, what GSM antenna are you using ?
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    XC9536 100 MHz Divider

    divide by 5 counter 100 mhz I've flashed the XC with the .JED file, it really works... It's generating both 9 MHz and 4 MHz outputs. Sorry, there must be some problem with my simulator.... Thank you ! :D
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    XC9536 100 MHz Divider

    free codes download for xc9536 Well, now it compiled, but it did not generated the 2 clock outputs on simulation , as you can see on the attached image.
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    XC9536 100 MHz Divider

    clock xc9536xl Thank's, but it didn't worked the way it's written: Tried to compile it on Xilinx ISE, verilog module, but got errors: module divby_11_22(clk, by_11, by_22); input clk; output by_11; output by_22; reg [4:0] counter; always @(posedge clk) begin if (counter == 5'd21)...
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    XC9536 100 MHz Divider

    verilog unexpected token I have this .JED file for programming my XC9536XL, it does divide the 100 mhz clock by 11 and 22, but i need to add some extra circuit on it. Does any1 knows if it's possible to disassemble it ?
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    XC9536 100 MHz Divider

    xc9536 Hi, i have a 100 MHz clock source and want to divide it by 11 to obtain 9.091 MHz and by 22 to obtain 4.54 MHz on different clock outputs, how can i do it ? module clkdiv(clk,q); input clk; output q; reg [1:0] COUNT; initial COUNT=0; assign q=COUNT[1]; always @(posedge clk)...
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    Verilog code for frequency divider (50 Mhz to 1 kHz)

    frequency divider Hello, i'm trying to divide 100 MHz clock by 11 and 22 to get 9.091 MHz and 4.545 MHz clock outputs. I'm using XC9536XL. I thought of using FDD (Double Edge Triggered Flip Flop), but it's not available to XC9536. How can i do it ? Thank's
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    Using Proteus Virtual terminal for sending data to PIC

    using virtual terminal in isis Great idea, i'm going to try that. Are there any tutorial on how to send bytes to the virtual terminal using that Pattern Generator Virtual Instument , i don't undestand how to do that. Thank's
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    Using Proteus Virtual terminal for sending data to PIC

    virtual terminal isis What if i need to send byte 0x00 ? THanks man

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