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Re: D flip flop
Using 5 FFs will result clk/32.
It seems that without combinational logic it is impossible to divide clk by 10. To minimize combinational logic a 3-bit LFSR can be used. Also an extra TFF with enable is required.
programable encoder
I need information about Programmable Encoder IC SCL1527. But information is placed only on Chinese sites.
If there is some datasheet even in Chinese please point the link.
Re: march test
There is a lot of informationabout about memory testing and especially about MARCH tests in Internet. At first you need to familiarize yourself with that background. After, if there still questions, I'm ready to answer on them
I believe that the optimal way is
always@(length or A) begin
case(length)
0 : B[0:15] = A[0:15];
1 : B[0:15] = A[1:15];
2 : B[0:15] = A[2:15];
...
15 : B[0:15] = A[15:30];
endcase
end
Re: Statement unreachable (Branch condition impossible to me
The fact that wr is declared as reg doesn’t mean that wr is FF. In your verilog code
the behaviour of wr is net (wire). So the code wr <= ~wr generates combinational loop, which is unacceptable in poor digital design.
Re: #delays in RTL
#delays are necessary in RTL when in projects are behavioral models of non-digital circuits, for instance memory. In memory behavioral models are setup, hold, recovery and other timing checks. The only way to provide this timing requirements is use #delay.
Another advantage...
I believe that it does not worth to change 8051 family. There are many 8051 microcontrollers equiped with different peripherials. You should just see MCU of another company.
I believe that it does not worth to change 8051 family. There are many 8051 microcontrollers equiped with different peripherials. You should just see MCU of another company.
Re: what is the typical read/write time of ram in ASIC and F
Read and write timings of embeded SRAM depends on the following parameters
- is it High Density or High Speed ?
many parameters.
- technology - 18um,13um,90nm,65nm
- quantity of bits in required memory
For high speed memories clock...
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