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Besides the specman e basic training.
You should lern to use eRM (e Resuse Methodology) and/or
sVM (system verification methdology), which are specman e advanced
application.
Re: 3D hardware
Of cause, VHDL can do this. Actually to design such a HW, VHDL/Verdilog is used.
But the big problem is from algorigthem->architecture-> RTL code-> Design
Graphics chip is very very complex, with often contains millions of gates.
Its function is not ONE BLOCK can do.
As far...
Re: is it necessary to run post_layout simulation for tape-o
For rtl level simulation, we should run sim and pass all the tests, which is called regression.
But gate level simulation, we may not run all the test, because of time. We just select some classical test to run
So for timing, we...
matlab for vlsi engineers
Matlab is for system modeling. It is used to verify and improve algorithm, to design the architecture.
But to design the Circuit, at least right now, no one can take place of HDL.
Re: Setup Hold time
Change rtl is the last way. You can imporve the timing through ECO, that is modifiy the netlist directly.
Setup time is more critical. One possible reason may be the load at that point is too heavy. So you can resove it in two way:
1. Replace the driving component with more...
why not use linux, it is more statle than windows.
you can install a virtual maching software on windows so that you can switch between linux and windows easily
Added after 4 minutes:
Search in the other forum, such as software upload/download, EDA books / doc upload/download.
You are in the...
To speak simply, eco is just change the design on netlist. So that you did not need to make the change from the rtl level.
ECO is used normally for timing closure. After P&R, you may still have some timing issue, such as heavy load, small buffer... then you can manually replace the component...
Re: why CLK & RESET pins should not be placed side by si
Power and ground are often used to resolve coupling. Not only for clock, but also for some often toggling signal. So in the meltal layer of IC, some time you can see
power or ground is lied between two signals. It is completely...
In my opinion, it is hard to do RTL level, or say standard cell based power analysis, for it is quite not accurate.
Take sysnosys compiler as example, normally it do the analysis in this way: cuculates the toogle times for each gate, get the related parameters from the lib,
multiple the power...
In front end asic design, normally only 30% time on coding, 70% time on functional verification. RTL code without verification is not really RTL code.
So it is a very important and mandatory process in asic design flow.
However in some small company, verification is very simple, just run...
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