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Thanks for the reply.
I agree with FvM, you are forgetting the blocking assignment.
But, anyway, my question was in the regards of hardware synthesis, not its behaviour. Makes sense on the verilog preprocessor/compiler/whatever to infer a three port AND gate.
My question was based in what...
Hi,
I'm not a Verilog guru but have some experience. My question is about how a always block is synthetized in hardware, not its behaviour.
let's suppose I've got an always block as:
input wire a, b, c;
output reg y;
always @(*)
begin
y = a;
y = y & b;
y = y & c;
end
Since I'm...
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