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vhdl loop synthesis
for synthesis tool in expression:
for i in x downto y loop
you should use constants x and y.
are you sure, that you expression:
for i in elite-1 downto 0 loop
contain constant elite, or maybe elite is signal? if it is, than is wrong.
real hold time always more than 0 ns. but the clock tree can have short delays (with comparison to data paths), than more or equal than hold time of real flip-flop elements of fpga. if this delay is equal to real hold time, that we have 0 ns hold time in fpga. if more, than we can have negative...
Help on Verilog-HDL
when altera quartus write this messages
("Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "Clock" is an undefined clock")
in mean, that you need to use the quartus assignments (map the "Clock" port to the one of the clk pin of...
only for post fit hdl simulation you can set the default values for all of states.
after simulation (after good result) you can delete the default state of states of the fsm.
matlab qam
1) generate input I/Q data in MATLAB
2) read this data in simulator (Modelsim, Aldec, etc.)
3) save output data of your design in simulator
4) compare the output data of hdl design and MATLAB model
Aldec and Modelsim also can work with MATLAB directly, but i don't know how
if you need to clear the register at the time, when optional increment isn't selected, use the synchronous clear
process
begin
if (rising_edge(clk)) then
if (increment=0) then
register <= 0;
else
register <= register + increment;
end if;
end if;
end process;
Time in Matlab
the time duration is not represent in matlab.
for example a = [1 0 1 1 0 0 0 1 1 1 0]; length(a) = 11;
sample time is 1us (for example)
summary: length of a is 11us
you can't say to matlab how to use your physical sample time. but you need to remember, than sample time is xx...
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