Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
verilog float
Hi all,
I want to test my floating point adder in verilog. For this I need to generate bit vector from "real". The is function "$realtobits" but this creates 64 bit vector from real. My fp adder is single precision so I need 32 bit vector.
May be someone knows how to create 32...
I forgot to mention that I'm interested in structured asic design tools.
As I understand I can use DC for sinthesis but after synthesis and before etools I need also 1 step (I thing this should be some kind of placement). And I dont know which tools can I use in this step?
Hi all,
I just looked into easic.com and found there design flow picture.
In that picture is shown that it is posible to make sinthesis using Magma or Synopsys. After synthesis next step is placement and optimization. But only Magma is shown there.
If someone has experienc in structured ASIC...
glitch in the clock
Hi,
To be honest I dont know what are Muler Gates :D (if you have some links it will be very appreciated :D)
I'm using asynchrous gates but there is not any loops.
It can be be synthesized I tried.
But I dont know how to check or constraint clock module. How can I be sure...
glitches on clock
It more simple then PLL.
I have 2 asynchronous clock inputs and 5 clock outputs.
It is just clock divider. It is not dificult module I understand. But it should be glitch free. I already designed the module and its is working with functional simulation.
But I dont know will...
clock glitch
Hi all,
I'm designing clock module for ASIC. This is my first experience in clock module design. For synthesis I'm using Design Compiler. I dont know how to give constraints for generated clocks. Can someone give me some info.
Also is it posible to check with Design Compiler...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
