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Hi vengatesh,
My problem is different.
I have two modules, first one is in 50 MHz, 2nd one is in 100Mhz.
i am sending one ctrl signal from 50Mhz module to 100Mhz module. that is high for one clock period of 50 MHz. If you sample tat ctrl signal in 100Mhz module that signal will be high for two...
Hi sivamani,
It is edge triggered.
let me explain it in more clear.
if one trigger comes from 50Mhz to 100Mhz, while reading the same trigger in 100Mhz it may think that it has received two times the trigger. so process will be initiated two times.
How to overcome this problem?
Hi friends,
I have a question realted to CDC.
if i transmit a enable signal from 50Mhz to 100Mhz, then one enable signal becomes 2 enable signal in the 100Mhz region.
which means the module which is working in 100Mhz will think like it will get 2 times trigger from 50Mhz.
Can you please...
In order to convert mat lab code into hdl code I have implemented accel dsp.
but after converting that code one file is missing named "pulse_gen".
just i have used inbuilt fir coding example which is given in the accel dsp example programs.
can u guide me pls.
thank u...
am having one more doubt in accel dsp
In order to convert mat lab code into hdl code I have implemented accel dsp.
but after converting that code one file is missing named "pulse_gen".
just i have used inbuilt fir coding example which is given...
hi
i struck with accel dsp sythesis code.
just i have used inbuilt acel dsp mat lab (fir) code.
after converting that code i have used that with xilinx 10.1
but one file is missing over there........... can any one guide me please........... thanks in advance.
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