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Recent content by Bond_2007

  1. B

    Design constraints for CPLD algorithms

    Re: RTOs and CPLD Any inputs??
  2. B

    What is the best VHDL book?

    ebook vhdl by bhaskar the best way is to do experiments.
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    Changing from ucontroller concept to VHDL

    if you are confident, FPGA/VHDL coding can be fun.
  4. B

    What is Combinatorial Logic?

    it needs only present input.
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    Where can I find DSP projects in FPGA?

    Re: DSP Projects in FPGA There are lot of examples/projects in xilinx web-site and www.opencores.org
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    Design constraints for CPLD algorithms

    Hello, I have question, we are using TI BIOS RTOs and we have CPLD interface to the DSP. This CPLD is used for increasing the IOs and hence what are design constraints a designer has to look into while designing CPLD alogrithms? The reason is, suppose CPLD is trying to get some data from IOs...
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    VHDL, CPLD code:Will this implementation works

    any other inputs are greatly appreciated. -B
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    VHDL, CPLD code:Will this implementation works

    Hello, I would like to use the following case statement: test_bits<bit1,bit0> case 00: Make IO output PIN 7 high. case 01: Make IO output PIN 8 high. If case 00 has ran, the IO PIN 7 is high, will it stays high even when case 01 is running? Is this a latch...
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