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Oh OK!
I feel like probing floating voltages is an important enough topic that it should be taught in schools. Unfortunately, it is not.
I actually don't really know the answer to those questions myself. You did a good job with the information that you had. I was impressed.
Perhaps someone...
One interesting note is that there is a small drop-off in current through R2. The small drop-off occurs before the SCR is triggered. The drop-off I believe is due to zener diodes DW1 and DW2 conducting and clamping the gate-source voltage of Q1, which is essentially Vaux.
Edit: I'm not...
Sorry to hear you burned up fuses! All part of the normal learning process. I can suggest a couple pieces of test equipment that might help when troubleshooting circuits like these. Unfortunately, some of the equipment is kind of expensive. A differential probe for measuring across circuit...
Nice analysis. I pretty much understand everything except for the self-oscillating part.
I attached a marked up the schematic with different section analyzed. How does the circuit oscillate? I assume at startup, the gate of Q1 is pulled up and charged through R1 and R7. This causes current...
That's a boot-strap capacitor. That capacitor is needed in order to drive the gate of the high-side MOSFET (i.e. HS-FET) to the proper voltage (Vgs>Vth) when the FET turns on. The boot-strap circuit maintains Vgs>Vth when the HS-FET turns on and it's source is pulled to the drain voltage...
The left charge pump doesn't double the voltage to -20 V. The left charge pump inverts the input voltage to -10V. That -10 V (across C2) is applied to a series regulator formed by a zener diode and PNP pass transistor.
When you take into account the zener voltage and Vbe of the transistor you...
Are you happy at your current job? Do you enjoy working with your present coworkers?
I was in the same boat you were at one time. I thought I wanted to do VHDL/SV for a living. I ended up doing it for two companies and to be honest, it wasn't all that great. Sitting in front of a unix...
OrCAD PSpice is this a Good Deal?
Been looking to improve my knowledge of schematic and PCB design tools. Anyone know if this is worth it? I know there are a bunch of free alternatives which is why I'm asking.
https://pages.ema-eda.com/Get-OrCAD-PCB-Design-Software
Also, if you only require low bandwidth (< 1Mb/s) you could use a UART or I2C interface. The interfaces are much simpler to design and only require two pins: UART (RX/TX) and I2C (SCL/SDA).
The LPC specification defines a clock up to 33 MHz. The LPC bus is relatively low bandwidth, well within the capabilities of modern FPGA's. Is there something special about what you're doing?
Here's the code for your falling edge detect. There's really not another way to do it. :thumbsup:
reg Rxd_Sync;
reg Rxd_Buf1;
reg Rxd_Buf2;
reg Rxd_Fall;
always @ (posedge clk) begin
Rxd_Sync <= Rxd;
Rxd_Buf1 <= Rxd_Sync;
Rxd_Buf2 <= Rxd_Buf1;
Rxd_Fall <= ~Rxd_Buf1 & Rxd_Buf2;
end
Early synthesis tools weren't capable of separating out registers from combinatorial logic, which is why designers used the 2-process approach, one process for registers and another for logic. Tools are much more capable now and more (most) people favour the one process approach. Also, the...
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