Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by bjbhargav

  1. B

    Information about MAGMA CTS commands

    Re: MAGMA CTS Hi buddy, You can find your answer in attached pdf, bj
  2. B

    Magma Blast Synthesis Question

    magma blast Hi buddy, In Magma You will have a gain (Virtually a Size) for each design cell untill real placement is done. Magma has an additional step called library preparation, in that magma decides gain for each cell available in library from tau(T) value derived from minimum size...
  3. B

    Optimization Power consumption using Design Compiler

    tutoriel power compiler Hi buddy, You can catch a tutorial on power compiler from the following link, **broken link removed** bj
  4. B

    Map netlist from GTECH to Technology library

    Hi, I am using synopsys DC ultra (topo) for synthesis with provided reference methodology by synopsys, However, aftert synthesis I got netlist with GTECH components, How can I map my design to Technology library ? Thanks, bj

Part and Inventory Search

Back
Top