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Hello,
I aim to design a wideband two stage Op-Amp. Now, Miller compensation is good but, kills the bandwidth. I have found, 'phantom zero' is one method which can be used to compensate the 2nd dominant pole in the loop. Can anyone suggest how to implement this in a two-stage Op-Amp?!
P.S> the...
Kindly help me with a suggestion. How can I calculate the load impedance given in the picture. I am designing a differential input and single ended output Op-Amp to drive this load. I need to know the load values, but I am not sure about if the capacitors are in series or parallel in the small...
Re: Common Mode Regulation in a LVDS Driver
Wonderful. I think you mean the pole created by the (Bond + Pack) Cap and the termination resistance at the output?! Why do we choose the common mode input for this compensation?! Is this because this is the high impedance node here?! So with minimum...
Re: Common Mode Regulation in a LVDS Driver
Ok. Thanks a Lot. Now Its clear.
P.S. the compensation by Rc and Cc, is this miller compensation?! If so what determines the value of Rc?!
Re: Common Mode Regulation in a LVDS Driver
Thanks for your reply. But my question is if the common mode regulation is only through negative feedback or is this some other special arrangement?! Sorry, I am not clear with that yet.
Common Mode Regulation in a LVDS Driver
Hi,
Can anyone highlight the common mode regulation circuit given in the picture is a negative feedback (always) or an occasional positive feedback?! I am bit confused with the case, if the common mode at the detector output is lower than the reference...
Hello,
I am very much pleased to know about the benefits of Negative Feedback and how it is used in conventional LVDS Driver Circuit. I am trying to design one for myself. But as per the negative feedback thery, the Open Loop Gain of the Amplifier/Core Module is normally very high. With...
Hi All,
Can anyone give me a ballpark idea of what is attenuation of a signal through an ideal channel (FR4) in a chip-to-chip serial link?! I am working with a 2.5 GHz frequency. In literture, I found for an ideal channel, it could be around 6 dB or more (but for 10 GHz frequency). I am...
Re: Two stage open loop comparator draw large instantaneous current
Even if I remove the Load Cap, but this circuit will drive another MOS Cap in the following stage. In my understanding, still this large spike current will be present, which could surge the overall network. Is there any more...
Re: Two stage open loop comparator draw large instantaneous current
We see the output M6 transistor source current (Is) in the figure. The circuit has capacitive load. Current flows through the load. The result is from transient simulation. You could check the circuit schematic in this link...
Two stage open loop comparator draw large instantaneous current
Hi,
I have a basic two stage open loop comparator circuit. While checking the dynamic power I found that in the comparator second stage, the source transistor (PMOS), is drawing large instantaneous current (glitch). See the...
I am trying. I am using multiple initial blocks in the testbench. This makes the structure bulky and introduce scheduling issues. Looping over sending data is fine. But additional control words are not done yet.. Since its an easy problem, I thought of asking, to know if there is a better approach.
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