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Recent content by birdiee470

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    What are the layout techniques used?

    Layout Techniques try to minimize your metal layer. because your contact create resistance and noise. Try to locate all your cell smartly and do the floor plan before start your layout,, Its very important.
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    Intel's "2000 packaging databook" (chapter on ESD)

    Re: esd yaa,,what is this all about,,put back that attachment so we can discuss it together,,
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    Questions for Instrumentation

    This web really can help **broken link removed**
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    how to convert 12v data signal into 5v

    drop 12v 5v you can use voltage divider..for resistor value,,calculate yourself
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    How does a capacitor charges and discharges?

    Capacitor capacitor chargers when you apply voltage across it and discharges when you remove supply voltage.
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    Analog and Digital Design

    both analog and digital is important in today technology, analog application is not that much to understand but quite difficult,,,but digital is very large area and quite easy,,, or you can combine to be mixed signal,
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    Who is your idole in Analog Design?

    David A. johns (I`ve meet him before, he is so genius)
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    What are the biggest design challenges when we move from 130 to 90 and 65?

    from 130nm to 65nm 65 nm tech only suitable for digital design,,, if you implement in analog design u will have trouble in noise and bandwidth,
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    What will be the future of the VLSI engineers ?

    future of vlsi dont be afraid to involve in VLSI because if you do. you are not part of us. moore`s law actually relate to the size of the device. but there are lot of topology and technique that we need to develop for achieve good performance,,that is more challange, moore`s law is only for...
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    MSN Messenger group discussion

    good idea,,why i never think of this before. what is the group name? i will join
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    diode connected capacitor?

    the diode resistance help to lead compensate the phase for better stability.refer ken martin text book pp. 240
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    Comparator inverter stage

    both inverter generate delay to your circuit. also can act as a buffer. attach design spec for further discussion. is has a relation with your transient time (slew rate, delay,rise time, fall time etc)
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    Who is your analog IC design engineer heroes (update)?

    Who is your analog IC design engineer heroes (update)? Pls describe your heroes.

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