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Recent content by birbal

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    [SOLVED] FPGA: Different behavior after synthesis

    Update: Modified the clock generation by using a register (instead of the combinational way) and this seems to solve the problem.
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    [SOLVED] FPGA: Different behavior after synthesis

    I kind of realized that is not an optimal way to generate a clock. But my question is how do I generate a 2 MHz based on the master 100 MHz? I would also like to be parametrizable...not always is going to be a 2 MHz, in some instances the freq might vary. I also tried with the pin name for...
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    [SOLVED] FPGA: Different behavior after synthesis

    I'm using a Digilent Nexys4 development board with Vivado v2017.1 and verilog for the code. My design uses a master clock (clk) of 100MHz. In of my modules I generate a 2 MHz clock (sclk) as follow: always @ (posedge clk) begin if (adc_en) begin if (clock_count < TICKS_SCLK -1)...
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    Preserving net naming in Synthesis using DC

    The answer is yes for both questions. I have the all the code and synthesis scripts. Also the sims works if I change the names in the test bench to mach the netlist new signals. The problem is next time when there are some more RTL updates, the tool might decide to optimize in a different way...
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    using if statement in verilog

    There is no point of checking the bit 49, class can be assigned to its value straight away. As simple as: assign class = svm[49];
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    using if statement in verilog

    Why are you make it overcomplicated? Why not: assign class = svm[49];
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    Preserving net naming in Synthesis using DC

    I'm tring to preserve a list of ports of a specific module in the hierarcy that I'm synthesising with Synopsys DC. This is required because I'm runing some simulations at the gate level and in the test-bench I'm using those signals. Before synthesis I run set_dont_touch on the nets I'm...
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