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Recent content by billkas

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    VHDL/Modelsim: simulation output to file?

    Hello everyone, Is there a way to create a simulation output file in VHDL? I'm using Modelsim. So far I've only found something about a TEXTIO package, but I'm not quite sure on how to integrate this into my testbench code (Google didn't help enough this time :-| ) Any advice would be...
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    Verilog code error I can't define!

    Thank you very much for your answers, I've found out what the mistake was! I'll post the right one asap!
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    Verilog code error I can't define!

    Thank you for the answer! I did exactly what you suggested, but still it won't compile :/
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    Verilog code error I can't define!

    Hello everyone! I'm a noob in Verilog and I've written this module: module databus_send(data_out, signature, data_send, data_last); output [31:0] data_out; output signature; input [31:0] data_send; input [31:0] data_last; integer i, count; assign count = 0; //hamming distance...
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