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Hi, i downloaded a freePDK45nm to use at synthesis and PnR.
In freePDK45nm, there are
- gscl45nm.db
- gscl45nm.lef
- gscl45nm.lib
... etc
During synthesis step, there was no problem because synthesis only need .db file.
But during PnR step, IC_Compiler need milkyway form and i dont have it...
First of all, thanks for your help.
If you don't mind can i ask question with more detail..?
My module is single cycle crossbar. The crossbar's max operate frequency are rapidly decrease when the number of in/output port of crossbar increase. I want to show above crossbar property myself.
So...
For example, i synthesized some module with 1GHz time constrain and there was no negative slack.
So, I did PnR also with 1GHz time constrain and there was negative slack.
In this case... should I synthesized module again with lower frequency? or it is enough just changing PnR time constrain?
Hi i'm using ASAP7 library (http://asap.asu.edu/asap/).
Actually, this is my first time using some kind of EDA tool... so the term which i used maybe wrong sorry.
Anyway what i want to know is
1. In "tech.lef" there are some code like this
2. In "stdcells.lef" there are some code like...
Hi, i'm trying to Place and Route some logic with innovus and i wonder about how can i change or fix the location of some modules.
Figure below is my base result. Module has 4 sub-modules. And the P&R result look like this.
So far, i am happy but i need some more... what i really want to do...
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