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Recent content by bigbro

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    Information about powerclamps in IC design

    Re: Powerclamp Power clamp is used for ESD protection. There are 2 blocks, one is ESD detection block and other one is big mos transistor between power and ground and it's gate should be connected to ESD detection block. The idea of ESD detection block is that ESD surge is faster rising time...
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    Why my chip can stablize soon only when GND floated?

    It looks like there is floating node in your database. If substrate is floating, the floating node would pull up easily. Also leakage should be increase under high light source. This is the reason you can reduce stabilized time, I think.
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    I/O transistor vs Analog transistor

    There is no difference of spice model. But some manufacture request lager IO MOS transistor length for ESD. Also there are alot of different design rule in the layout side.
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    Can I connect guard ring or chip guard ring to the ground ESD of the chip?

    Re: guard ring If there is any noise block, you should use back to back diode to connect each block. If noise level is higher than one diode turn-on vtg, use more series diode.

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