Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by bharath9

  1. B

    default values of wire and reg

    hi, what are the default values of wire and reg?
  2. B

    better ways to clock divisions

    we can also divide using counter logic but when to use counter logic?
  3. B

    better ways to clock divisions

    hey guys, which is better way to divide the clock either using pll(ip's) or writing code algorithm. when to use pll? when to use algorithm?

Part and Inventory Search

Back
Top