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Recent content by bharadwaj.cv

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    Doubt about process parameters while reading the 40nm technology manual

    These are the doubts I have. In the technology manual they specify that the CMOS process has "Six to eight copper metal levels, including up to seven 1x, 1 relaxed-pitch 2x and two 6x metal level(s)". what does 1x and 2x specify here and what is relaxed pitch? It also says the CMOS process has...
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    basic doubt on ferrite core's working

    I have heard that ferrites are used in transformers and other applications. And that they are used for concentrating flux. Is this right? What property helps them do this? What is the relation between that property and the magnetic flux? Can you kindly provide me the answer and if possible a...
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    [SOLVED] Coil design and air box in HFSS

    Hello, I want to design coils in HFSS. A transmitting coil and a recieving coil for wireless power transfer and see the radiation pattern. My frequency is 450 KHz. I am doing this in ansoft, so I have to have an airbox right? But lamda for my case is 666m. lamda/4 is 666/4m which should be the...
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    intutitive explanation of the impedance seen at the source of a diode load

    There will always be a difference between the drain and the bulk right, whether or not the bulk is grounded??? Did you mean source??? Even then I did not clearly understand.....can you explain in little more detail....
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    intutitive explanation of the impedance seen at the source of a diode load

    In the book "Design of Analog CMOS integrated circuits by Razavi", on page 53 and 54 (section 3.2.2) he says that when looking into the source of a diode connected load the impedance seen at source of M1 is lower when body effect is included. I understand the explanation provided by him using...
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    Error in CST rearding meshing

    In CST EM studio i get an error which says "some degenerated tetrahedrons exist in subdomain 18 background material. Generating a finer mesh for this region or removing smaller features might help". I have two questions. 1) How do I view the subdomains. And check for the solution to my problem...
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    calculation of inductance using ansoft hfss

    I have designed a coil, i need to calculate the inductance value using ansoft. I have done the hand calculation, but i need to verify it with ansoft...how do I do this??? is there a way??? thanks
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    Coil design using Ansoft HFSS

    Hello, I want to design a coil for transmitting power into the brain (<50Hz frequency) using transcranial magnetic stimulation. Can I do it in ansoft HFSS?? If so, how should I give the excitations. If not, what other software can I use??? thanks in advance.
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    Spiral antenna simulation in HFSS

    can some one please upload the spiral patch antenna files for hfss on this site...thanks :) if not possible then can u kindly send the file to bharadwaj.cv@gmail.com
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    variable reference voltage

    I want to generate a variable reference voltage. It should be such that the user can choose the input value(since my circuit is meant to be a product). This can be done by a knob or a keypad and the voltage should remain at the value he wants, till he wants. How do I do this. One option is a...
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    clock generator using ramp with VH and VL

    thanks..............................................................
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    clock generator using ramp with VH and VL

    How do you generate the ramp in a digital way..any circuits that can do that???any references????....thanks
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    clock generator using ramp with VH and VL

    If i want a variable duty cycle clock, I can use a ramp generator and a comparitor with variable reference right?? In that case, how lower a frequency can I go to?? I want to generate a clock which has a frequency that can vary from 1-60Hz with duty cycle variable..is it possible by this method...
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    How to get 1/3 duty cycle from a 50% duty cycle clock?

    Hey I want to generate a programmable duty cycle from 50% duty cycle signal. But my signal is in the order of 2-50Hz. Since I want to do this on an ASIC, I think i can use an produce a programmable delay and AND the original signal with the output of the programmable delay....but how to create a...
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    How to convert 0 to VDD to -VDD/2 to +VDD/2

    is there any specification on what kind of capacitance this should be, for me to get -VDD/2 to VDD/2. or can any cap do this? when I try out in cadence, with a 1 pf cap for a square wave at 400kHz, it totally subtracts the signal by -1. Say I give in 0 to 1, square wave with 50% duty cycle, it...

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