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Recent content by bhanuriramesh

  1. B

    How many MOS transistors are required to implement full adder?

    Re: INTERVIEW QUESTION we cant implement a fulladder sum with 6 transistor.... min num of transistors req r 28.........................
  2. B

    plz..i need some pdfs on timing analysis of digital ckts

    i am unable to find the materials on timing analysis.. plesase someone load the e buks...... thanx in advance
  3. B

    Mentor Graphics Introduction to VHDL

    Re: FPGA FAQ good material Added after 1 minutes: plz sendme some topics on static timing analysis
  4. B

    can a latch have setup and hold time violation...

    materials uploaded are really extra ordianry
  5. B

    requet for the Jtag tutorial.

    good material
  6. B

    Gated clock module for reducing power consumption

    Re: about Gated clock material is reaaly good... thanx for uploading such material
  7. B

    How to calculate minimum skew and proceed with duty cycle other than 50% in STA?

    Re: doubts in sta thanx friend..ur material seems to be very gud.... Added after 1 minutes: could u attach some more materials on sta........... thanx in advance
  8. B

    Help with interview question #2

    setup time isuseful in calculating the critical fresuency
  9. B

    How many MOS transistors are required to implement full adder?

    Re: INTERVIEW QUESTION min num of 28 transistors are required to omplement fulla dder
  10. B

    Good tutorial for TCL

    ur tutorial is gud. seems gud for starters
  11. B

    Suggest me some projects on FIFO

    could any one suggest me some projects on fifo... and also suggest me some live architectures presently ind using
  12. B

    discrete fourier transform basics

    dft + fastscan + basics could u pllz telll me the tool used for dft... and is this tool available for free
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