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Recent content by bhanu.somisetty

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    [SOLVED] SRAM butterfly curve

    Greetings.. can please help me,draw butterfly curve,iam doing project on SRAM thanks bhanu
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    How to reduce the leakage current in CMOS Analog Switch??

    Hi iam using TG(Transmission gate) for mux.Can any one help with how to reduce leakage current for TG?? THanks BHanu
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    A CMOS Voltage Reference Based on Weighted Vgs for CMOS Low-Dropout Linear Regulators

    Hi, Iam trying to implement a design in the below paper: "A CMOS Voltage Reference Based on Weighted Vgs for CMOS Low-Dropout Linear Regulators" So i need to find out temperature coefficients of the threshold voltages for n and p-type CMOS transistors. Can any one help me in finding out the...
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    Spectre error for TSMC65nm

    Hi When i try to simulate inverter for TSMC65 nm i got the below error: Error found by spectre during hierarchy flattening. Error (SFE-1996) "../crn65lp_v1d5.scs" 58496 : parameter 'noian_25': unknown parameter name 'par1fn_mc' found in expression Can any one help... Thanks
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    Flip Flop area optimization....

    Hi thanks for the reply in terms of circuit design of FF's can you give me some guide lines... any method to follow to design a standard cell FF for area optimization??? Thanks
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    Flip Flop area optimization....

    Hi Can anyone explain me how to optimize a Flip Flop for area??? Thanks
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    Standard cell library development in TSMC90nm...

    Hi I am new to standard cell design.. can any one help me how to start developing a standarad cell libary in TSMC 90nm from scratch? 1)To develop INV family (INV1x,INv2x..INV16x..)how to decide on the specification(delay,slew,poweretc..),W/L? 2)To develop complex gates like Flip-Flops how to...
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    how are MOSFET device models derived....PDK's

    Thanks a lot..if you have any material on how PDK's are made,i request you to pls upload...
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    how are MOSFET device models derived....PDK's

    Hi all, any one tell me "how are PDK's made,for Transistors?i meant to ask how are mos device models made,which are used for circuit simulations? Thanks
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    SAR ADC hold time simulation...

    Hi all, I am working on 12 bit sar adc,how to simulate the hold time? Thanks Bhanu
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    startup ciruit ...how does the node 1 go to vdd...?Thankyou...

    Hi Thanks for the explanation.Would you pls let me "why the M3 and M4 gate voltage goes to VDD?"
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    startup ciruit ...how does the node 1 go to vdd...?Thankyou...

    Hi All... In the attachment,the startup circuit is used to avoid a condition "where the gate voltages of transistor M1,M2 become zero and M3,M4 become VDD and the circuit doesnt work". Can anyone explain,why the gate voltages of M1,M2 go to zero and M3,M4 go to VDD? Thanks a lot....
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