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Recent content by bh_letters

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    Measuring CPU time in Modelsim

    modelsim cpu Hi, Are there any utilities or options in ModelSim for recording the CPU time taken for simulation. I am trying to measure CPU time taken for my verilog design simulation in Modelsim. Does any of the verilog system tasks record CPU/System time. Thanks
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    Sync-on-Green Timing Diagram

    sync on green Hi, Can you please share timing details/diagrams for Sync-on-Green format, where synchronization (HSYNC, VSYNC) signals are embedded along Green signal. Thanks
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    Range of FIR filter co-efficients

    Hi, I am trying to design a general purpose 8-tap FIR filter. What is the general range of coefficients for any application? is it from [-1 to 1] or [0 to 1] ...? This filter will be used in interpolation applications with no signal gain. Thanks
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    Can decimal numbers be used for simulation purpose

    You can represent decimal numbers in exponential form, which can be either 32 bit or 64 bits depending on the range you want to cover. You also need special hardware that will recognise these numbers as floating point numbers and not as intergers. Logic that process floating point numbers.
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    Any free simulators for SystemVerilog?

    free systemverilog simulator Hi, Are there any free simulators for SystemVerilog? Does Modelsim XE support SystemVerilog simulations? Regards
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    Floating point representation in HDL

    $realtobits Hi, How are floating point numbers represented in HDL (verilog or vhdl)? If some one can explain with the addition of 2 floating numbers that would be great. Thanks
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    Designing 8-bit signed multiplier using 4-bit multiplier

    Hi, How do we design 8-bit signed multiplier using 4-bit signed\unsigned multipliers? Thanks
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    about FIFO,uses LFSR/Gray for read/write pointers

    I do not have enough points to view the attached document, so please let me know, what it says.
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    about FIFO,uses LFSR/Gray for read/write pointers

    Address generation using LFSR is less expensive than address generation using counters. LFSRs generate address in random sequence but in a unique order, which depends on the initial seed value. If we use same seed value for read address generator and write address generator, the reading sequence...
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    optimal way to generate two complement of a number

    I meant integer when I said number. I am looking for optimal circuit for representing an integer in its two's complement form.
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    optimal way to generate two complement of a number

    Hi, Which is an optimal way to generate two complement of a number using logic gates? thanks
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    Connecting two bidirectional ports in verilog

    Hi, I have two modules and each has a bidirectional (inout) port. Now I need to connect these ports. Both the modules use the same signal to determine the direction of data flow. If enable is low, module A acts as source and module B acts as destination. If enable is high, module B acts as...
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    API for writing data to Cypress EZ-Host through USB port.

    Hi, I need to write a program that detects EZ-Host attached to the PC and write data into EZ-Host memory. Some advice on this or link to sample programs would be greatly appriciated. Thanks
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    Device driver to send data through USB Port

    Hi all, I am trying to write a device driver in C so that it can send data to a USB Interface chip (Cypress CY7C67300). I have few questions regarding this: Does Cypress chips have a seperate library for building device drivers? will the device drivers for different chips be different...
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    verilog task for detecting end of file

    Hi, Are there any verilog system tasks available for detecting EOF. If ther aren't any, how can I detect EOF using available system tasks. Thanks
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