Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Erik,
I see your point and agree. The original post was asking about op amp inputs and in that case, active loads are the way to go unless you want the absolute lowest noise possible and you are willing to make significant compromises to get it.
Indeed, the CML gates I was referring to had...
I disagree that a CML gate is not an analog circuit. To design on you need to worry about GBW, noise, swing, PSRR, gm, and the like. But depending on your definition, sure. You could think of it as a digital circuit designed by analog designers in an analog way.
I also disagree with you...
Two more reasons:
1. Resistor-loaded diff pairs have lower noise for a given headroom. Some older low-noise opamps had resistor loaded front ends.
2. Resistor loaded diff pairs switch faster because of lower capacitance for a given resistance. CML logic is *usually* (but not always) done...
Re: Caluclating power consumption in cadence spectre
It's quite simple. Plot the current drawn by the mirror from the supply and multiply it by the power supply. For a current mirror you can even do it with a dc analysis and display the current id on the device. Multiply that by VDD and that...
For this reason you should make a guard ring out of your substrate taps, ideally around each individual BJT as well to catch injected minority carriers.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
