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Recent content by benthefpga

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    VHDL generics: how to make a port of width log2(generic)

    This is a great tip! But if 'width' is a generic, where do you declare the subtype 'data_word_t' such that it can be used in the port declaration for 'input'? I was under the impression subtype declarations had to be in a package in order to use them on a port, but packages don't have access...

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