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Recent content by bellona

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    [SOLVED] How to assign different terminal for the two ends of one metal wire in Calibre PEX?

    I'm layouting an LNA with SiGe BiCMOS process. Since the Emitter resistance degenerates the gain, I'd like to double connect the NPN's emitter, as shown in this picture: The problem is: How can I assign different terminal for the two ends of the Emitter metal (marked with red arrow)...
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    [SOLVED] How to do copper pour with cadence virtuoso?

    Thanks, erikel. I'm experimenting with Cadence's Routing IDE embeded in Virtuoso Layout GXL now. This router has the capability to do copper pour , though it's called power and ground stripes in the router.
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    [SOLVED] How to do copper pour with cadence virtuoso?

    Thanks for the reply, erikl. As to fringing capacitance, I figured out that won't hurt me much - In the process i'm using, when a signal line runs parallel with a ground plane with a separation of 10um between them, the fringing capacitance will be about 1fF per 20um of line run. I've seen some...
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    [SOLVED] How to do copper pour with cadence virtuoso?

    Hi, this is trivial in PCB design, but i don't know how to do this with RFIC design in cadence virtuoso, and google didn't return any useful results. I think Copper pour is quite useful for maintaing a CPW enviorment for transmission lines and it will also help meeting CMP metal density...
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    pex extraction wrong mult and fingers on MOS

    Hi, I suggest you switch to spctre or hspice instead. Calibreview is prone to these bugs. I've encountered similar problems before: https://www.edaboard.com/threads/168656/#post710199 Attactched is a tutorial written by erikl about post simulation from a spectre netlist, hope that would help.
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    Dummies for Resistors

    I think you need dummy resistors for diffused resistors as well, to make sure your working devices receive the same diffusion inteactions with their neighbours, as clarified in the book " The art of analog design, 2nd Edition" section 7.2.7. But i think poly resistor are better suited for matchings.
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    Dummy resistor to be ignored in Calibre LVS run

    I've tried to use the switches 'RC' & 'RE' in the 'Filter Unused Device Options' in my calibre tools, but the extrator still extracts those shorted dummy capacitors and resistors in my layout. At the end i have to delete those LVS marking layers for resistors and capacitors in my layout. In my...
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    when layout, what happen to the metal wire go through devece

    Re: when layout, what happen to the metal wire go through de well, the experiment in the aforementioned paper does show that metal 2 did have much less impact on matching than metal 1. As explained by the authors in another paper 'Characterization of Systematic MOSFET Current Factor Mismatch...
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    Pls check if latchup issue exists in this layout (Taped out)

    Re: Pls check if latchup issue exists in this layout (Taped Hi prcken, thanks for the reply. I agree with you that this might not be called latchup in this particular case, 'substrate debiasing' should be more appropriate. But i think substrate debiasing still involves current injecting into...
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    Pls check if latchup issue exists in this layout (Taped out)

    Re: Pls check if latchup issue exists in this layout (Taped Thanks, erikl. I'll try this out and will let you know if i find some meaningful results. BTW, do you have some relevant material about manually adding those parasitic BJTs that i can reference? Thank you! Thanks for your reply...
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    when layout, what happen to the metal wire go through devece

    For hydrogenation, since the hydrogen compensation is introduced near the end of process when the formation of metal system is completed, it doesn't matter much which layer the metal is in. Higher layer metal might introduce less stress gradient, which i'm not sure about.
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    when layout, what happen to the metal wire go through devece

    Routing of metal wire will affect the matching through stress gradient and hydrogenation, and i think it would somewhat alter thermal gradients if there exists any. Metal wire should not route over MOSFET active region if precisely matching is needed. And the wiring adjacent to matched MOSFET...
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    Pls check if latchup issue exists in this layout (Taped out)

    Re: Pls check if latchup issue exists in this layout (Taped Thanks for your reply, erikl and dick_freebird. In the process i'm using, the extractor didn't bother to extract parasitic BJTs at all. BJTs have to be labeled with a LVS_BJT layer to help extractor finding them and users are only...
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    Pls check if latchup issue exists in this layout (Taped out)

    Re: Pls check if latchup issue exists in this layout (Taped Hi erikl, thanks for your reply. I tried to add these backgate resistance in schematic and the result is the same. guess it's hard to simulate latchup purely from schematic? Now i found the PTAP associated with MN0 and MN1 isn't right...
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    Pls check if latchup issue exists in this layout (Taped out)

    Hi, everyone. One of the op-amps in my chip isn't functioning all right. The opamp is a fully differential opamp with folded cascode PMOS input stage. The Pre and Post-simulation shows nothing wrong, it's schematic is: I'm using a 0.35um 2p4m salicide process with non-epi substrate, VDD is...
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