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i have selected all the nets and set the paths as false paths it worked for the design, but i really dont understand why it worked? if the intra clk path error is between some clk and register D then we should choose it as multi cycle path, if the intra clk path error is between some register...
hello guys,
i have done a bd design in xilinx vivado 2015.4, it has generated the bit stream and i have tested the functionality of the design in my fpga, but it has WNS = -1, and TNS = -55, how to solve the timing error problem, it is saying the path source and destination ,one...
created a bd for zedboard, have to dump on zynq 706 ? how?
hello guys,
I have created a bd design for zedboard and verified it, now i want to dump the bd design onto zynq zc706 board , how to do it , do i need to create a seperate project for zynq zc package and create a bd from...
Re: how to use "block mem gen" in vivado IP as an axi mode and stand alone mode ?
ya ya keeping it in bram controller mode and pulling the portb out , i can use it in native mode.
Re: how to use "block mem gen" in vivado IP as an axi mode and stand alone mode ?
i want to write data to the bram memory from an axi interface through port A, and read in native mode through port B, cant i do that ???
Re: how to use "block mem gen" in vivado IP as an axi mode and stand alone mode ?
I mean clearly, whether i can choose the mode as bram controller and connect the port A to the bram ctrl and port B directly to other IP's.
how to use "block mem gen" in vivado IP as an axi mode and stand alone mode ?
hello friends,
I'm using a dual port block memory generator, how to use "block mem gen" in vivado IP as an axi_mode through port A and as a stand_alone mode in port B, can we configure block mem gen...
it is functioning under axi_m_clk only i didnt mention, kept it simple, is he counting the number of representation of the std_logic_vectors, means making (8 downto 0) then (9 downto 0) ....and so on?? Ok what is the meaning of the second if statement?
process(M_AXI_ACLK)...
hello every one, can anyone please tell me what is the value of write_index in the 1st if statement and in the second if statement? and what does the statement STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8)) mean, does it mean we shud consider vectors from 100 upto 8? kindly reply
signal write_index ...
i have used vio (virtual start and stop bits) to control start and stop bits of traffic generator, hence we can make stop bit zero and start bit one again and make the transaction whenever i wish to, but i am not getting the data generated in sequential order and it is generating random data...
Thanks for the reply, yes i was able to connect it by expanding the gpio pins and connecting it to start stop, i have tested the transaction from axi traffic gen to bram by exporting the design to SDK, I want to test the function of axi gpio, that gpio is not dedicated external pins, and how do...
1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits.
2)I want to...
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